Today, there is a consistent demand for lower power consumption in a wide variety of CMOS integrated circuits and many of these integrated circuits include at least one prior art CMOS analog circuit built with transistors operating at 1.2 Volts (V).
FIG. 1 shows a prior art transconductance amplifier as a Gm tuned circuit that is the one example of a prior art CMOS analog circuit built with transistors operating at 1.2 V, where Gm is a measure or estimate of the transductance of the analog circuit. Typically, the Gm tuned circuit is configured with the Gm of the input transistors set based upon Gm=Iref/DeltaV using feedback and the tail current Itail will change so that the relationship Gm=Iref/DeltaV is supported.
FIG. 2 shows a prior art example of the GM tuned circuit as a CMOS amplifier including Pmos transistors P1 and P2 and Nmos M1 and M2, as the transductor with the tail current Itail being sourced by an NMOS transistor Mb. In steady state, the transistor Mb will provide just enough tail current so that Gm=½ (Gm1+Gm2)=Iref/DeltaV and the tail current is set by the voltage between the gate and source of Mb Vgs(Mb)=V0. Thus V0 sets the tail current and it must also be large enough to keep M2 and Mb in saturation.
Consider FIGS. 1 and 2: Assume that M2 and Mb require a saturation voltage of 200 milliVolts (mV) each, implying that V0 must be at least 400 mV. Further assume that Mb is a low voltage device configured to operate at 1.2 Volts. Then its threshold voltage will likely be about 300 mV and its Voltage between gate and source (Vgs) will be anywhere from 300 mV to 500 mV depending upon the required current Itail. It is possible that Vgs(Mb) may not be enough to support proper Direct Current (DC) biasing of M2 and Mb.
The problem comes when the devices M2 and Mb each require a saturation voltage of 200 mV. If Mb is a low voltage device, operating at 1.2V for example, its threshold voltage will be about 300 mV and its Vgs will be between 300V and 500 mV depending on the required Itail across Mb. This leads to the possibility the circuit will fail because Vgs(Mb) may not enough to provide proper DC bias to M2 and Mb.
ITAIL is an important currant source because the current sunk by it helps to determine the overall tranconductance of the amplifier. In the implementation shown in FIG. 2, the first voltage VO may be used to bias ITAIL through the gate voltage Vgs of the transistor Mb. Assuming a saturation voltage VDS may be about 200 mV, then VO will be around 400 mV. Note that the transistor Mb may not be operating in saturation, but rather in the “analog” region. That is, Vgs>VTH, but not so great as to put Mb in saturation.
As the operating power supply voltages are pushed lower by advancing technology, the operating point VO may also be pushed lower. Like a stack of dominos, VO affects the bias of the transistor Mb, which affects transconductance and overall operation of the circuit.
For example, the problem in the prior art becomes worse in a telescopic CMOS amplifying stage as shown in FIG. 3. The amplifier of FIG. 2 has been refined to include a telescoping stage adding Nmos transistors M3 and M4. Now V0 needs to support the DC bias of 3 MOSFET transistors Mb, M2 and M4. If Mb is a 1.2 V device, then its Vgs will be less than required for V0 to provide proper DC biasing to Mb, M2 and M4.
One way to solve this uses a level shifter to offset the first voltage VO to a second voltage, VTH of Mb. FIG. 4 shows an approach known in the prior art that employs a level shifter with a Vx across itself, so that V0=Vx+Vgs(mb) when the circuit is in equilibrium. While this works, it adds a level shifter requiring more power and has done nothing to stop leakage from M2. It also adds complexity and tends to increase the die area required when used in integrated circuits.